The present invention relates to solid-state image pickup devices including semiconductor image sensors of, for example, CCD (Charge Coupled Device) type image sensors.
The semiconductor image sensors such as CCD type image sensors, MOS type image sensors, etc. are presently applied to most of image input devices. In recent years, the MOS (Metal Oxide Semiconductor) type image sensors have been reevaluated since the sensors have the advantages that the power consumption is small and that the sensors can be formed by using the same CMOS (Complementary MOS) technology as that for the peripheral circuits. On the other hand, in terms of image quality, the CCD type image sensors have been still widely applied to image input devices intended for high resolution since dark current and/or fixed pattern noises are low.
FIG. 8 shows a circuit of the charge detection section in a conventional CCD type image sensor. The conventional CCD type image sensor includes a horizontal CCD 101 that transfers a signal charge, a detection diode 102 that converts the charge transferred by the horizontal CCD 101 into a voltage with use of a detection capacitor 103 (value thereof: CFD), a source follower circuit 104 whose input section is connected to the detection diode 102, and a reset transistor 105 that discharges the transfer charge from the horizontal CCD 101 to a reset drain RD. The source follower circuit 104 includes an amplification transistor 106 and a constant-current load transistor 107.
In the CCD type image sensor, subsequently to the source follower circuit 104, an output circuit, which includes an amplifier for output impedance conversion and so on, is connected so as to output signals to the outside of chip. However, the output circuit is not shown in the circuit diagram of FIG. 8.
Explanation is hereinbelow given as to operations per pixel cycle (1CLK (clock)) of the conventional CCD type image sensor. As shown in FIGS. 8 and 9, φH1 is at High level during a time T1. Therefore, no charge is transferred from the horizontal CCD 101 to the detection diode 102. As a result, the transfer charge is accumulated under the φH1 gate. On the other hand, φR is also at High level, and thereby a voltage of the detection diode 102 is fixed to a voltage of the reset drain RD.
During a time T2, φR is at Low level, and thereby the voltage of the detection diode 102 enters a floating state.
During a time T3, φH1 is at Low level, and thereby the charge accumulated under the φH1 gate is transferred under an output gate OG to the detection diode 102. The transferred charge is converted into a voltage with use of the detection capacitor 103 in the detection diode 102.
If a difference signal between the time T2 and the time T3 is read by a subsequent clamp circuit, differential amplifier, CDS (Correlated Double Sampling) circuit or the like, then an effective signal is read. Given that the transfer charge is Qsig, an output voltage Vsig is expressed as:Vsig=G·Qsig/CFD  (Ex. 1)where CFD represents the value of the detection capacitor, and G represents the gain of the source follower circuit, the gain having a value of about 0.8 to 0.9.
Generally, a voltage of about 1 V is applied to the output gate OG, a voltage of about 12 V is applied to the reset drain RD and the output drain OD, and a direct-current voltage of about 0.8 V is applied as a bias.
However, the conventional CCD type image sensor causes the following problems as to the construction and operation thereof. That is, given that CFD is a value of the detection capacitor 103 detected by detection diode 102, when signal charge Qsig from the horizontal CCD 101 is converted to a voltage signal Vsig, a charge-voltage conversion efficiency η is expressed as:η=Vsig/Qsig=G/CFD  (Ex. 2)
In the source follower circuit 104, the gain G is about 0.8 to 0.9. Therefore, so long as the circuit is the source follower circuit, the gain cannot be higher than 1.0. As the result, in order to enlarge the charge-voltage conversion efficiency η, the value CFD of the detection capacitor 103 needs to be reduced. CFD is a sum of a source junction capacitance of the reset transistor 105, a gate capacitance of the amplification transistor 106 and a junction capacitance to the substrate. However, the value of the gate capacitance of the amplification transistor 106 is dominative. Therefore, in order to reduce the gate capacitance of the amplification transistor 106, the size of the amplification transistor 106 is designed to be reduced as far as possible.
Meanwhile, the power of thermal noises and 1/f noises generated in the amplification transistor 106 are respectively expressed per unit frequency as:thermal noise power ∝1/gm∝1/√(CoxW/L)  (Ex. 3)1/f noise power∝1/(CoxLW)  (Ex. 4)
In the above expressions, gm represents the transconductance of the amplification transistor 106, W represents the gate width of the amplification transistor 106, L represents the gate length of the amplification transistor 106, and Cox represents a gate oxide film capacitance per unit area.
That is, the noises tend to relatively increase when the size of the amplification transistor 106 is reduced.
Accordingly, in order to reduce the noise components, a method for enlarging Cox by reducing the thickness of the oxide film is proposed (refer to JP H06-216385A).
However, when Cox is enlarged, the gate capacitance increases. Thereby, the charge-voltage conversion efficiency η is reduced on the contrary. That is to say, improvement in the charge-voltage conversion efficiency η and reduction in the noises generated in the amplification transistor 106 have a trade-off relationship.